The present application relates to semiconductor wafer level packaging technology and, more particularly, to fan-out wafer level packaging processes in which infrared radiation is employed to release a silicon (Si) handler wafer from a fan-out wafer level package.
Smartphone, tablet and laptop computer consumers are depending on their electronic products to be small, light, and fast. Wafer Level Packaging (WLP) allows these products to be handheld sizes with high-quality graphics, instead of large bulky devices. Demand for WLP is not only driven by the need to shrink package size and height, but also for performance reasons. There are two general categories of WLP technologies: ‘fan-in’ and ‘fan-out’ wafer level packages (WLPs).
Conventional fan-in WLPs are formed on the dies while they are still on the uncut wafer. The final packaged device is the same size as the die itself. Singulation of the device occurs after the device is fully packaged. Thus, fan-in WLPs are a unique form of packages and have the distinction of being truly die-sized. WLPs with fan-in designs are typically employed for low input/output (I/O) count and smaller die sizes.
Fan-out WLP (or FOWLP) typically starts with the reconstitution or reconfiguration of individual dies to an artificial molded wafer. The molded reconstituted wafer forms a new base to apply a batch process that features build-up and metallization constructions, as in the conventional fan-in WLP back-end processes, to form the final packages.
FOWLP technology was developed to provide a solution for semiconductor devices requiring higher integration levels and a greater number of external contacts. FOWLP provides a smaller package footprint with higher input/output along with improved thermal and electrical performance.
In FOWLP technology, the semiconductor dies are typically formed above a glass handler wafer. Glass handler wafers have their limitations in terms of mechanical properties, thermal conductivity as well as semiconductor equipment compatibility. Also, silicon wafers are more desirable as a handler because they have higher mechanical strength than glass handler wafers and perform better in wafer warpage control. However, current silicon handler solutions require mechanical peeling for release, which can introduce high stress on FOWLP. As such, low-stress release of a silicon handler substrate from a FOWLP is needed. Also, needed is method in which the handler substrate can be released from a FOWLP by high-throughput.